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| 19-1634; Rev 0; 1/00 KIT ATION EVALU ABLE AVAIL 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters General Description Features o Meet Fibre Channel Jitter Tolerance Requirements o 3.0V to 3.6V Operation o Internally Terminated Data and Clock I/O o Reference Clock Not Required o Frequency Lock Indication o Low Power Consumption 215mW at 3.3V (MAX3770) 190mW at 3.3V (MAX3771) MAX3770/MAX3771 The MAX3770 is a 2.125Gbps Fibre Channel repeater IC. The MAX3771 provides a pin-compatible solution for 1.063Gbps Fibre Channel. Both devices are optimized for use in Fibre Channel arbitrated-loop applications and operate from a 3.3V supply. The MAX3770 is compatible with Fibre Channel jitter tolerance requirements and can recover data signals with up to 0.7 unit interval (UI) jitter. The circuit's fully integrated phase-locked loop (PLL) provides a frequency lock indication and does not need an external reference clock. The MAX3770 provides low-jitter CML clock and data outputs. To reduce the external parts count, all signal inputs and outputs are internally terminated. The MAX3770/MAX3771 are available in 16-pin QSOP packages. Pin Configuration TOP VIEW ________________________Applications 2.125Gbps Fibre Channel 1.063Gbps Fibre Channel Fibre Channel Storage Systems Storage Area Networks Fibre Channel Hubs FILT+ 1 FILT- 2 GND 3 IN+ 4 IN- 5 16 LOCK 15 CLK+ 14 CLK- MAX3770 MAX3771 13 CLKEN 12 GND 11 OUT+ 10 OUT9 LOCKEN Ordering Information PART MAX3770CEE TEMP. RANGE 0C to +70C PIN-PACKAGE 16 QSOP GND 6 VCC 7 VCC 8 MAX3771CEE* 0C to +70C 16 QSOP *Future product--contact factory for availability. QSOP Typical Application Circuit 0.22F IN+ INVCC LOUT+ MAX3750 MAX3751 SEL LOUT- LIN- LIN+ OUT+ OUTGND Zo = 75 Zo = 75 IN- IN+ LOCK VCC MAX3770 MAX3771 LOCKEN CLKEN FILT+ FILT- LOUT+ LOUT- LIN- LIN+ CLK+ CLKOUT+ OUTGND Zo = 75 Zo = 75 IN+ INVCC OUT+ MAX3750 MAX3751 SEL OUTGND 3.3V 0.1F 3.3V 0.1F 3.3V 0.1F PORT BYPASS CIRCUIT DATA REPEATER PORT BYPASS CIRCUIT ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +5.0V Pin Voltage Levels (IN+, IN-, FILT+, FILT-, LOCKEN, CLKEN, LOCK) ....................-0.5V to (VCC + 0.5V) LOCK Output Current .........................................-1mA to +10mA CML Output Currents OUT+, OUT-, CLK+, CLK-.................................................-22mA to +22mA Continuous Power Dissipation (TA = +70C) 16-Pin TQFP (derate 6.7mW/C above +70C)..........533mW Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-55C to +150C Processing Temperature (die) .........................................+400C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CLKEN = VCC Supply Current (Note 1) CLKEN = GND Differential Voltage Signal at OUT or CLOCK Output Current at OUT or CLOCK LOCK Output Low LOCK Output High Differential Input Voltage Swing Input Common-Mode Voltage Voltage at FILT+, FILTCLOCKEN and LOCKEN Input Current Differential Input Resistance Differential Output Resistance OUT+, OUT-, CLK+, CLK-5 132 132 150 150 RLOAD = 150, Figure 1 Sum of IOUT+ and IOUTIOL = +1mA IOH = -100A 2.4 200 VCC - 0.45 VCC - 1.03 +5 181 181 2200 CONDITIONS MAX3771 MAX3770 MAX3771 MAX3770 400 MIN TYP 63 81 57 67.5 780 10.5 0.7 91 1000 mVp-p mA V V mVp-p V V A 112 mA MAX UNITS Note 1: Supply current includes output currents. 2 _______________________________________________________________________________________ 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER OPERATION AT 2.125Gbps Edge Speed Random Jitter Generation at Data Output Deterministic Jitter Generation 20% to 80% Input = K28.7+ (Note 2) TA = +25C Input = CRPAT (Note 3) Input = CRPAT (Notes 3, 5) TA = +25C TA = +25C (Note 5), input = CJTPAT (Note 6) Input = CJTPAT (Note 6) 50 Input = K28.7+ (Note 2) Random Jitter Generation at Data Output Deterministic Jitter Generation TA = +25C Input = CRPAT (Note 3) Input = CRPAT (Notes 3, 5) TA = +25C TA = +25C (Note 5), input = CJTPAT (Note 6), BER = IE-12 Input = K28.5 (Note 4) Input = CRPAT (Notes 3, 5) f = 42.5kHz f = 635kHz f = 5MHz Input = K28.5 (Note 4) Input = CRPAT (Notes 3, 5) f = 85kHz (Note 7) Jitter Tolerance CDR Lock Time from Start Propagation Delay Clock to Q Delay OPERATION AT 1.063Gbps 3.9 2.3 3.4 17 36 3.1 0.54 0.3 UI psRMS ps/rms psp-p psp-p f = 1270kHz (Note 7) f = 10MHz 1.5 0.1 135 3.4 2.3 3.9 15.6 27 4.22 0.89 0.36 4.4 1000 240 1500 300 ms ps ps UI 170 5.3 3.1 7.3 22 48 psp-p psRMS ps CONDITIONS MIN TYP MAX UNITS MAX3770/MAX3771 Jitter Tolerance Note 2: K28.7+ pattern: 0011111000 Note 3: Compliant random pattern (CRPAT) in hex: Pattern No. of Occurrences 3EAA2AAAAA 6 3EAAA6A5A9 1 86BA6C6475 D0E8DCA8B4 7949EAA665 16 72319A95AB 1 C16AAA9AA6 1 Note 4: K28.5 pattern: 00111110101100000101 Note 5: Random and deterministic jitter generation at 2.125Gbps is measured with 0.38UI deterministic jitter, and 0.22UI random jitter (BER = 1 x 10-12) applied to the input. Random and deterministic jitter generation at 1.063Gbps is measured with 0.18UI deterministic jitter, and 0.08UI random jitter (BER = 1 x 10-12) applied to the input. Jitter tolerance at 2.125Gbps is measured with 0.38UI deterministic jitter and 0.22UI random jitter (BER = 1 x 10-12) applied to the input. Jitter tolerance at 1.063Gbps is measured with 0.18UI deterministic jitter, and 0.08UI jitter (BER = 1 x 10-12) applied to the input. Note 6: Compliant jitter tolerance pattern in hex (CJTPAT): Pattern No. of Occurrences 3EAA2AAAAA 6 3EAAA6A5A9 1 871E3871E3 41 871E3870BC78F4AAAAAA 1 AAAAAAAAAA 12 AAA15555E3 871E3871E1 1 AB9C9686E6 1 C16AAA9AA6 1 Note 7: Jitter tolerance measurements at 85kHz and 1270kHz are limited by test equipment. Actual jitter tolerance > indicated. _______________________________________________________________________________________ 3 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 Pin Description PIN 1 2 3, 6, 12 4 5 7, 8 9 10 11 13 14 15 16 NAME FILT+ FILTGND IN+ INVCC LOCKEN OUTOUT+ CLKEN CLKCLK+ LOCK FUNCTION PLL Loop Filter Connection. Connect a 0.22F capacitor between FILT+ and FILT-. PLL Loop Filter Connection. Connect a 0.22F capacitor between FILT+ and FILT-. Ground Positive CML Data Input (Figure 3) Negative CML Data Input (Figure 3) Supply Voltage When this input is forced high, the lock indicator is enabled. Ground for normal operation. Negative 75 CML Data Output (Figure 4) Positive 75 CML Data Output (Figure 4) When this input is forced high, the clock output is enabled. Ground for normal operation. Negative 75 CML Clock Output (Figure 4). Enabled when CLKEN is forced high; disabled when CLKEN is forced low. Positive 75 CML Clock Output (Figure 4). Enabled when CLKEN is forced high; disabled when CLKEN is forced low. Frequency Lock Indicator. High level indicates the PLL is frequency-locked. Disabled when LOCKEN is forced low. The output of the LOCK pin may chatter when large jitter is applied to the input. Typical Operating Characteristics (VCC = +3.3V, TA = +25C, unless otherwise noted.) MAX3770 JITTER TRANSFER MAX3770/1 toc01 MAX3770 JITTER TOLERANCE CJTPAT VCC = 3.3V CF = 0.1F MAX3770/1 toc02 MAX3770 RECOVERED DATA AND CLOCK SIGNALS MAX3770/1 toc03 5 0 JITTER TRANSFER (dB) -5 -10 -15 -20 -25 1k 10k 100k 1M 10M 100M CJTPAT VCC = 3.3V CF = 0.1F 10 SINUSOIDAL INPUT JITTER (UI) VCC = 3.3V CJTPAT DATA 1 0.1 FIBRE CHANNEL SINUSOIDAL JITTER MASK CLOCK VCLK100ps/div 0.01 1G 10k 100k JITTER FREQUENCY (Hz) ADDITIONAL 0.6UI DJ AND RJ APPLIED ABOVE 10MHz 1M 10M 100M JITTER FREQUENCY (Hz) 4 _______________________________________________________________________________________ 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 VOUT+ 200mVp-p MIN 500mVp-p MAX VOUT- (VOUT+) - (VOUT-) 400mVp-p MIN 1000mVp-p MAX Figure 1. Example of Output Signal with RLOAD = 150 0.22F FILT+ LOCKEN VCC FILT- LOCK IN+ 150 IN- LOCK PHASE/FREQ DETECTOR LOOP FILTER MAX3770 MAX3771 VCO TTL 75 75 CLK+ CLKCLKEN VCC 75 75 OUT+ D LATCH Q OUT- Figure 2. Functional Diagram _______________________________________________________________________________________ 5 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 Detailed Description Figure 2 shows the functional diagram of the MAX3770 Fibre Channel repeater IC. The MAX3770 consists of a fully integrated phased-lock loop (PLL), CML input and output buffers, and a data latch. The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). The input and output signal buffers employ low-noise CML architecture and are terminated on-chip. VCC ESD STRUCTURES 1k 1.5nH IN+ 0.2pF 0.4pF 1.5nH 0.2pF 0.4pF 75 75 VCC - 0.450V PACKAGE Phase and Frequency Detector The phase/frequency detector generates an output signal that reflects the phase relationship between the incoming data and the internal clock generated by the VCO. Data recovery is accomplished by feedback in the PLL, which drives the error voltage to zero, aligning the falling edge of the recovered clock to the center of the data eye. The phase frequency detector generates a frequency lock indication that can be monitored at the LOCK pin (Table 1). When the PLL is frequency-locked onto the incoming data, lock transitions high. Figure 3. Input Structure VCC VCO and Latch The fully integrated VCO contains an internal current reference and filter circuitry to minimize the influence of V CC noise. The VCO is trimmed to 2.125GHz (MAX3770) and creates a clock output with frequency proportional to the control voltage applied by the loop filter. Data recovery is accomplished by using the recovered clock signal to latch the incoming data to the CML output buffers, significantly reducing the output jitter. PACKAGE 75 75 1.5nH OUT+ 0.4pF 1.5nH 0.4pF ESD STRUCTURES OUT0.2pF 0.2pF Applications Information Figures 3 and 4 show models for the MAX3770/MAX3771 inputs and outputs, including package parasitics. Figure 5 shows typical 50 termination applications. 10.5mA Design Procedure The MAX3770's performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. All IN, OUT, and CLK pins can be connected with 0.1F or 0.01F coupling capacitors. If DC coupling is desired, pay particular attention to the DC voltage and current requirements at the pins of interest (see DC Electrical Characteristics). The MAX3750/MAX3751 port bypass circuit can be DC-coupled to the MAX3770/MAX3771 repeater. A 0.22F capacitor should be used for the loop filter. Figure 4. Output Structure Control Functions The lock enable (LOCKEN) and clock enable (CLKEN) pins can be configured to control the PLL's clock. Table 1 shows the operational modes available. 6 _______________________________________________________________________________________ 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 75 DIFF (LOOKING OUT) 0.1F Zo = 50 300 IN+ OUT+ MAX3770 MAX3771 IN0.1F 100 DIFF (LOOKING IN) 150 DIFF (LOOKING OUT) 43 Zo = 50 176 IN+ OUT+ MAX3770 MAX3771 IN43 100 DIFF (LOOKING IN) OUT43 176 43 Zo = 50 OUT0.1F 0.1F Zo = 50 300 Zo = 50 Zo = 50 Zo = 50 Zo = 50 Figure 5. 50 Termination Applications Chip Topography FILT+ FILTGND IN+ INGND VCC VCC 0.067" (1.702mm) LOCK CLK+ CLKCLKEN GND OUT+ OUTLOCKEN 0.066" (1.676mm) Table 1. Output States When Using Control Functions INPUT PIN LEVEL LOCKEN CLKEN GND GND VCC VCC GND VCC GND VCC OUTPUT FUNCTION LOCK CLOCK Disabled Disabled Enabled Enabled Disabled Enabled Disabled Enabled TRANSISTOR COUNT: 1217 SUBSTRATE CONNECTED to GND _______________________________________________________________________________________ 7 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 Package Information QSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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